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                                                  RK3368

                                                  RK3368 is a low power, high performance octal-core Cortex-A53 processor for mobile phones
                                                  型號:RK3368
                                                  品牌:ROCKCHIP
                                                  封裝:TFBGA453
                                                  批號:15+
                                                  庫存:700

                                                  規格書(Datesheet):RK3368.PDF 點擊下載

                                                  商品信息

                                                            RK3368 is a low power, high performance processor for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates octal-core Cortex-A53 with separately NEON coprocessor. (點擊即可咨詢芯片詳細信息

                                                  RK3368’s Features
                                                  1、 MicroProcessor
                                                  - Octal-core ARM Cortex-A53 MPCore processor, a high-performance,
                                                  low-power and cached application processor
                                                  - Two CPU clusters, with four CPU core for each cluster, One cluster is
                                                  optimized for high-performance(big cluster) and the other is optimized for
                                                  low power(little cluster)
                                                  - Full implementation of the ARM architecture v8-A instruction set, ARM Neon
                                                  Advanced SIMD (single instruction, multiple data) support for accelerated
                                                  media and signal processing computation
                                                  - ARMv8 Cryptography Extensions
                                                  - In-order pipeline with symmetric dual-issue of most instructions.
                                                  - Harvard Level 1 (L1) memory system with a Memory Management Unit
                                                  (MMU).
                                                  - Level 2 (L2) memory system providing cluster memory coherency, including
                                                  an L2 cache.
                                                  - Include VFP v3 hardware to support single and double-precision add,
                                                  subtract, divide, multiply and accumulate, and square root operations
                                                  - SCU ensures memory coherency between the four CPUs
                                                  - CCI400 ensures the memory coherency between the two clusters
                                                  - Integrated 32KB L1 instruction cache , 32KB L1 data cache with 4-way set
                                                  associative
                                                  - 512MB unified L2 Cache for big cluster, 256KB unified L2 Cache for little
                                                  cluster
                                                  - Trustzone technology support
                                                  - Full coresight debug solution
                                                  - Ten separate power domains for every core to support internal power switch
                                                  and externally turn on/off based on different application scenario
                                                  - One isolated voltage domain to support DVFS
                                                  - Maximum frequency can be up to 900MHz@0.9V for Cortex-A53 big cluster
                                                  - Maximum frequency can be up to 750MHz@0.9V for Cortex-A52 little
                                                  cluster
                                                  2、 Memory Organization
                                                  - Internal on-chip memory
                                                  - External off-chip memory①
                                                  3、Internal Memory
                                                  - Internal BootRom
                                                  - Internal SRAM
                                                  4、External Memory or Storage device
                                                  - Dynamic Memory Interface (DDR3/DDR3L/LPDDR2/LPDDR3)
                                                  - Nand Flash Interface
                                                  - eMMC Interface
                                                  - SD/MMC Interface
                                                  5、System Component
                                                  - CRU (clock & reset unit)
                                                  - PMU(power management unit)
                                                  - Timer
                                                  - PWM
                                                  - WatchDog
                                                  - Bus Architecture
                                                  - Interrupt Controller
                                                  - DMAC
                                                  - Security system
                                                  6、 Video CODEC
                                                  - Shared internal memory and bus interface for video decoder and encoder②
                                                  - Embedded memory management unit(MMU)
                                                  - Video Decoder
                                                  - Video Encoder
                                                  7、 HEVC Decoder
                                                  - Main/Main10 HEVC/H.265 decoder
                                                  - 4k@60FPS (core clock@300Mhz)
                                                  - Support up to 4096x2304 resolution
                                                  - Support up to 100Mbps bit rate
                                                  - Embedded memory management unit(MMU)
                                                  - Stream error detector (28 IDs)
                                                  - Internal 128k cache for bandwidth reduction
                                                  - Multi-clock domains and auto clock-gating design for power saving
                                                  8、 JPEG CODEC
                                                  - JPEG decoder
                                                  - JPEG encoder
                                                  9、 Image Enhancement
                                                  - Image pre-processor
                                                  - Video stabilization
                                                  - Image Post-Processor (embedded inside video decoder)
                                                  10、 Graphics Engine
                                                  - 3D Graphics Engine :
                                                  - Base handheld architecture fully Microsoft® DirectX™ 9.3, OpenGL®
                                                  3.1, and OpenGL ES 3 compliant
                                                  - Support for pull-model attribute evaluation
                                                  - Tile-based deferred rendering architecture with concurrent processing
                                                  of multiple tiles
                                                  - Multi-threaded Unified Shading Cluster (USC) engine
                                                  11、Video IN/OUT
                                                  - Camera Interface(interface only)
                                                  - Camera Interface and Image Processer(Interface and Image Processing)
                                                  - Display Interface
                                                  12、HDMI
                                                  - Single Physical Layer PHY with support for HDMI 1.4 and 2.0 operation
                                                  - Support HDCP 1.4
                                                  - Support HDCP 2.2
                                                  13、MIPI_DSI/LVDS/TTL combo PHY
                                                  - MIPI_TX
                                                  - LVDS
                                                  - TTL
                                                  14、MIPI_CSI PHY
                                                  - Embedded one MIPI_CSI PHY
                                                  - Support 4 data lane, providing up to 4Gbps data rate
                                                  15、eDP PHY
                                                  - Support 4Kx2K @ 30fps
                                                  - Compliant with eDP TM Specification, version 1.1
                                                  - Up to 4 physical lanes of 2.7/1.62 Gbps/lane(HBR2/HBR/RBR)
                                                  - RGB, YCbCr 4:4:4, YCbCr 4:2:2 and 8/10/12 bit per component video format
                                                  - Encoded bit stream (Dolby Digital, or DTS) – IEC61937 compliant
                                                  - Support VESA DMT and CVT timing standards
                                                  - Fully support EIA/CEA-861D video timing and Info Frame structure
                                                  - Hot plug and unplug detection and link status monitor
                                                  - Support DDC/CI and MCCS command transmission when the monitor
                                                  includes a display controller.
                                                  - Supports Panel Self Refresh(PSR)
                                                  16、 Audio Interface
                                                  - I2S/PCM with 8ch
                                                  - I2S/PCM with 2ch
                                                  - SPDIF
                                                  17、 Connectivity
                                                  - SDIO interface
                                                  - High-speed ADC stream interface
                                                  - TS interface
                                                  - Smart Card
                                                  - GMAC 10/100/1000M Ethernet Controller
                                                  - SPI Controller
                                                  - Uart Controller
                                                  - I2C controller
                                                  - GPIO
                                                  - USB Host2.0
                                                  - USB OTG2.0
                                                  - HSIC Interface
                                                  18、 Others
                                                  - Temperature Sensor(TS-ADC)
                                                  - SAR-ADC(Successive Approximation Register)
                                                  - eFuse
                                                  - Operation Temperature Range:-40C to +85C
                                                  - Operation Voltage Range:Core supply: 1.0V (±10%) IO supply : 3.3V or 2.5V or 1.8V (±10%)
                                                  - Process :GlobalFoundry 28nmSLP
                                                  - Package Type
                                                                    TFBGA453LD(body: 19mm x 19mm; ball size: 0.4mm; ball pitch:0.8mm)
                                                   
                                                  RK3368’s Block Diagram
                                                   RK3368's Block Diagram
                                                  RK3368’s Package

                                                   RK3368's PackageRK3368's Package

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